1. Field of the Invention
The invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a dummy gate structure and a method of forming the same.
2. Description of the Prior Art
As the size of the field effect transistors (FETs) is continuously shrunk, the development of the planar FETs faces more limitations in the fabricating process thereof. In order to improve such fabricating limitations, three-dimensional or non-planar transistor technologies, such as fin field effect transistor technology (FinFET) have been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However, with the demands of miniaturization of semiconductor devices, the width of each fin-shaped structure narrows and the spacing between the fin shaped structures shrinks. Thus, forming fin shaped structures which can achieve the required demands under the restrictions of miniaturization, physical limitations and various processing parameters becomes an extreme challenge.